The present invention relates to high speed input/output (I/O) controllers, and more particularly, to a method of handling interrupts using an interrupt migration method.
As is well known in the art, the function of I/O processing has grown increasingly complex. Users of computer systems and network systems compete for resources simultaneously. This competition, for example, is sometimes by order of request and sometimes based on a priority basis. And through it all, it is the CPU function that must arbitrate the momentary allocation of resources to a specific user, provide synchronization and control over the various devices involved, and keep track of the actual data transfer so that the job may ultimately be "put back together," and so that the user can be assured that his or her program actually receives all inputs and transmits all outputs--each to or from the proper place and in the proper order.
As is also known in the art, in normal operating environments, a central processing unit (CPU) may be simultaneously communicating with one or more of its external devices (of same or different types), but seldom with all and usually not in any predictable pattern. This requires the establishment of timing and control procedures to effect a proper connection and to provide "momentary interface synchronization" for individual message pulses.
For communication (or transmissions) initiated by devices, the device must signal the processor to interrupt the program flow and alert the operating system that an external device needs attention, much like a doorbell rings or a telephone signals that someone outside wishes to communicate with those within. In both cases, action must be taken in a timely fashion to ensure that no signal is unintentionally disregarded and no data are lost, a distinct possibility that occurs when the CPU is simultaneously communicating with several high speed devices.
An I/O controller, such as a disk controller or a network controller, typically moves data between a disk subsystem or a network subsystem, and other units of a computer system. When inbound data is received from the subsystem, the controller typically transfers the data to a main memory unit, to await further processing. The memory unit may be connected to a system bus, which is shared by other units of the computer connected thereto. Outbound data, retrieved from the memory unit, are subsequently transferred by the controller to the subsystem. A direct memory access (DMA) function located on the controller directs movement of data through the controller.
The I/O controller manages its input and output data streams by moving the data streams from/to a memory via DMA. The I/O controller reports an event on completion of a DMA operation by posting an interrupt. For example, the event may be the completion of transmitting a packet of data or receiving a packet of data. As data rates handled by the I/O controller increases, the amount of interrupts increases. The overall result may be system performance degradation.
As is also known, when the CPU receives an interrupt, it does an operation called "context switching," before executing an interrupt handler program or scheduling the interrupt for future processing. The context switching operation is time consuming, since the CPU typically stores all data needed to continue execution of the program once it returns from the interrupt routine. As a result, the CPU is utilized in a less effective manner, since normal flow of the program is disrupted causing instruction cache misses to occur.
In a system that includes I/O controllers that send a high interrupt rate, the CPU may be overwhelmed, since it will be using a high percentage of its time for interrupt handling. The result is degradation of overall system performance.